1. Field of the Invention
The present invention relates to a semiconductor integrated circuit apparatus which forms elements such as a central processing unit, peripheral units and memory units which are components of a computer and, more particularly, a semiconductor integrated circuit apparatus such as, for example, a semiconductor integrated circuit apparatus for use in a parallel computer and aerospace applications which are required to provide high reliability and performance.
2. Description of the Related Art
Lately, computers have been remarkably advanced in their performance. A representative circuit technology which has supported such progress of computer performance is found in completely complementary static CMOS (complementary metal oxide semiconductor) circuits. The completely complementary static CMOS circuit requires less power consumption and excels in high efficiency of integration, as compared with a bipolar transistor circuit. As is well known, such CMOS circuits are comprised of a P-type logic block composed of P-type MOS transistors and an N-type logic block composed of N-type MOS transistors which are connected in series, wherein the two logic blocks operate complementarily. A rise time of an output signal depends on the characteristics of the PMOS transistors and a fall time of the output signal depends on the characteristics of the NMOS transistors. Generally, a gain factor xcex2 of the PMOS transistors is smaller than the gain factor xcex2 of the NMOS transistors. Accordingly, if channel widths and channel lengths of the PMOS transistors and NMOS transistors are designed to be equal, the rise time of the output signal is longer than the fall time. On the contrary, the channel widths of PMOS transistors need to be larger than the channel widths of NMOS transistors to make the rise time and the fall time of the output signal equal, resulting in an increase of input capacitance and area.
A CMOS domino logic circuit is one example of a circuit for solving a problem of the above-described completely complementary static CMOS circuit (R. H. Krambeck, Charles M. Lee and Hung-Fai Stephen Law, xe2x80x9cHigh-speed Compact Circuits with CMOSxe2x80x9d, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-17, NO. 3, 1982). An example of such a CMOS domino circuit is shown in FIG. 9. The CMOS domino circuit is a dynamic circuit which forms a logic circuit using only NMOS transistors. Accordingly, a delay in signal propagation depends on the characteristics of the NMOS transistors. In the CMOS domino circuit, there is no problem of an increase of the delay time resulting from the P-type logic block which is the problem in the completely complementary static CMOS circuit. Since the logic is formed only with the NMOS logic block and the input capacitance and the parasitic capacitance in the circuit, the operation is carried out at a high speed and the area is small.
However, the CMOS domino circuit includes the following three problems. The first problem is that, since the CMOS domino circuit is a dynamic circuit, it is very susceptible to xcex1 particle noise. A circuit diagram and operating waveform for such a circuit are shown in FIG. 10. The CMOS domino circuit precharges a clock signal to be entered into the circuit during a period when the clock signal remains at a low level, and the logic is propagated during the period when the clock signal remains at a high level. When an input signal is at a low level while the clock signal remains at a high level for a logic decision, a node point A remains at a high level and the charge at the point A is dynamically maintained. At this time, if xcex1 particles hit the drain of the N-type transistor 100, the charge at the point A is discharged and the potential level at the point A lowers. There is no path for charging the discharged electric charge. Therefore the potential level, which has been lowered, does not return to the previous level, and a faulty operation results.
The second problem is that the CMOS domino circuit, which is a dynamic circuit, is susceptible to leakage current noise. When an input signal is at a low level while the clock signal remains at a high level for determination of the logic, a node point A remains at a high level and the charge at the point A is dynamically maintained. At this time, the charge at the point A is discharged by the leakage current through the N-type transistor and the potential level at the point A lowers. There is no path for charging the discharged electric charge and therefore the potential level, which has been lowered, does not return to the previous level and a faulty operation results.
The third problem is a problem related to a charge redistribution effect as shown in FIG. 11. A capacitance of the node point A of the CMOS domino circuit is assumed as CA and a capacitance of the node point B is assumed as CB. If the input signal A is at the low level and the input signal B is at the high level in the logic decision period 1, the potential of the node point A remains at the high level xe2x80x9cVddxe2x80x9d and the potential of the node point B remains at the low level xe2x80x9c0Vxe2x80x9d. Since NMOS transistors 101 and 102 are kept off during the precharging period, the potential at the node point A remains at the high level xe2x80x9cVddxe2x80x9d and the potential at the node point B remains at xe2x80x9c0Vxe2x80x9d. When the input signal A is set to the high level in the logic decision period 2, the NMOS transistor A turns to ON, the charge is redistributed between the node point A and the node point B and the potential of the node points A and B is xe2x80x9c(CA/(CA+CB)) Vddxe2x80x9d. When the capacitances of CA and CB are substantially equal, the potential of the node points A and B is xe2x80x9c(xc2xd) Vddxe2x80x9d which leads to a faulty operation.
As a means for solving the problems of the CMOS domino circuit such an, for example, xcex1 particle noise, leakage current and charge redistribution effect, there has been proposed a method for adding a feedback type pull-up PMOS transistor 103 shown in FIG. 12. The electric charge to be discharged due to xcex1 particle noise and charge redistribution effect is compensated by weakly pulling up the point A of the dynamic node with the feedback type pull-up PMOS transistor 103. However, when the N-type logic block 104 draws out the charge at the node point A to a low level, the feedback type pull-up PMOS transistor 103 prevents this drawing-out operation. The through current flows to cause not only the power consumption to increase but also the switching speed of the circuit to remarkably lower. Accordingly, this means impaired high speed operation and is therefore unsuitable for a system which requires high speed operation of the circuit.
A static circuit for speeding up the completely complementary static CMOS circuit by precharging in advance of the output is disclosed in Japanese Patent Application Disclosure Gazette HEI. 2-277315. However, this circuit comprises circuits for precharging the output to a high level voltage and circuits for precharging the output to a low level voltage which are alternately series-connected and operated and therefore PMOS transistors and NMOS transistors alternately operate and the signals cannot be propagated only through NMOS transistors.
As described above, though the CMOS domino circuit is proposed as a circuit which operates at a higher speed than the completely complementary static CMOS circuit, the CMOS domino circuit includes a problem that it is susceptible to noise. On the contrary, if the feedback type pull-up PMOS transistor is added to make the circuit less susceptible to noise, the high speed operation of the circuit is impaired. To solve these problems, the present invention is intended to provide compatibility of high noise tolerance and high speed operation.
An object of the present invention is to provide a circuit which is not susceptible to noise and which operates at a higher speed than the conventional completely complementary static CMOS circuit.
A semiconductor integrated circuit apparatus according to the present invention has a plurality of complementary static logic circuits which are series-connected to first and second sources and a potential setting means which is connected to respective output parts of these complementary static logic circuits and which sets outputs of the output parts to the second potential in synchronization with the clock signal.
An embodiment of the potential setting means has a precharge means, which is connected to the first source and sets the output part of the complementary static logic circuit to the first potential in synchronization with the clock signal, and an inverter for setting the output part, which is set to the first potential by this precharge means, to the second potential.
In addition, it is preferable that timing control means for controlling an operation timing of the complementary static logic circuit in synchronization with the clock signal is provided between the complementary static logic circuit and the second source.
According to another embodiment of the semiconductor integrated circuit apparatus of the present invention, the semiconductor integrated circuit apparatus is provided with a plurality of complementary MOS transistor blocks having MOS transistor blocks of one conductivity type which are connected to the first source and the output parts and which receive input signals supplied, and MOS transistor blocks of the opposite conductivity type which are connected to the output parts and the second source and which receive the input signal. The plurality of these complementary MOS transistor blocks are series-connected so that the output signal of the complementary MOS transistor block of the front step serve as the input signal for the complementary MOS transistor block of the rear step. A potential setting means for setting the output signal of the complementary MOS transistor block of the front step to the second potential is provided between complementary MOS transistor blocks, and the signals are propagated from the complementary MOS transistor block of the front step to the complementary MOS transistor block of the rear step by the operation of the opposite conductivity type MOS transistor.
In addition, according to a further another embodiment of the semiconductor integrated circuit apparatus of the present invention, the semiconductor integrated circuit apparatus has a plurality of logic blocks which substantially comprise MOS transistors and at least one of the plurality of these logic blocks has a plurality of complementary MOS transistor blocks which respectively comprise one conductivity type MOS transistor block, which is connected to the first source and the output part and receives input signals, and the opposite conductivity type MOS transistor block, which is connected to the above-described output part and the second source and receives input signals. The plurality of complementary MOS transistor blocks are series-connected so that the output signals of the complementary MOS transistor block of the front step serve as the input signals for the complementary MOS transistor block of the rear step. A potential setting means for setting the output signals of the complementary MOS transistor block of the front step to the second potential in synchronization with the clock signal is provided between these complementary MOS transistor blocks. Signals are propagated from the complementary MOS transistor block of the front step to the complementary MOS transistor block of the rear step according to the operation of the opposite conductivity type MOS transistor block.
A latch circuit which operates in synchronism with the clock signal to be entered into the potential setting means of the logic block of the front step is provided between these logic blocks. An inversion signal of a clock signal entered into the logic block of the rear step is used as a clock signal to be entered into the logic block of the front step.
An outline of an example of a preferable circuit to which the present invention applies is shown in FIG. 1. This example circuit comprises a P-type logic block 105 which is composed of at least one P-type field effect transistor having a source electrode and a drain electrode, which are series or parallel-connected between a first power supply terminal 111 and a first internal terminal 109, and a gate electrode connected to an input terminal 108 and an N-type logic block 106 which is composed of at least one N-type field effect transistor having a source electrode and a drain electrode, which are series or parallel-connected between a second power supply terminal 112 and the first internal terminal 109 and a gate electrode connected to the input terminal 108, wherein the P-type logic block 105 and the N-type logic block 106 form a completely complementary static CMOS circuit which performs complementary operation. An inverter circuit 138 is series-connected between the first internal terminal 109 and an output terminal 139. Further, an N-type field effect transistor 137 having a source electrode and a drain electrode, which are connected to the N-type logic block 106 and the second power supply terminal 112, and a gate electrode into which the clock signal CK is entered is connected therebetween, and a first precharging device 107 for precharging the first internal terminal 109 to the first power supply potential is connected between the first power supply terminal 111 and the first internal terminal 109. The clock signal CK is entered into the control terminal of the precharging device 107.
Operation and effects of the present invention are described below, referring to FIG. 1. In FIG. 1, the potential of the first power supply terminal 111 is assumed as Vdd (hereafter referred to as xe2x80x9chigh levelxe2x80x9d) and the potential of the second power supply terminal 112 is assumed as Vdd (hereafter referred to as xe2x80x9clow levelxe2x80x9d). When the potential of the clock signal CK110 is a low level, the precharging device 107 turns on, and the potential of the first internal terminal 109 is set to the high level and the potential of the output terminal 139 is set to the low level. Since the N-type field effect transistor 137 remains off even when the signal of the input terminal 108 changes during a period when the potential of the clock signal CK remains at the low level, the potential of the output terminal 139 remains unchanged at the low level. If the input signal changes from the low level to the high level when the potential of the clock signal CK has the high level and the N-type field effect transistor 137 is on, the N-type logic block 106 turns on, the potential of the first internal terminal 109 changes to the low level and the potential of the output terminal 139 changes to the high level. On the contrary, even though the input signal changes from the high level to the low level and the P-type logic block turns on, the potential of the output does not change since the first internal terminal is originally set at the high level. Accordingly, the output signal changes in accordance with the input signal only when the input signal changes from the low level to the high level and the N-type logic block turns on. As described above, the gain factor xcex2 of the N-type field effect transistor is higher than the gain factor xcex2 of the P-type field effect transistor and, in other words, this circuit in which signal propagation is delayed only when the N-type logic block 106 turns on operates at a high speed. The P-type field effect transistor which forms the P-type logic block suffices to compensate the leakage current of the N-type logic block 106 and the external noise current and has nothing to do with propagation of input signals. For this reason, the P-type field effect transistor does not require a large load driving force and therefore the channel width of the P-type field effect transistor which forms the P-type logic block can be designed to be sufficiently smaller than the channel width of the N-type field effect transistor. In other words, an input capacitance of the circuit according to the present invention and the junction capacitance of the P-type field effect transistor can be reduced to enable high speed operation.
The other effect of the circuit of the present invention is high noise tolerance. In the circuit according to the present invention, the P-type logic block 105 which is comprised of P-type field effect transistors and the N-type logic block 106 which is comprised of N-type field effect transistors are series-connected between the first power supply terminal 111 and the second power supply terminal 112 as described above, and the P-type logic block 105 and the N-type logic block 106 form the completely complementary static CMOS circuit which performs complementary operation. Accordingly, the circuit according to the present invention does not dynamically maintain the charge, and thus differs from the CMOS domino circuit shown aa the above-described example of the prior art. Then, even though the leakage current, xcex1 particle noise, charge redistribution effect or noise due to the power supply line and the signal line occurs in the circuit according to the present invention, the P-type logic block 105 and the N-type logic block 106 which perform static complementary operation always pull up or down the first internal terminal 109 to the first or second power supply potential to enable minimization of the noise. Thus, even if the output potential is inverted by noise, the output potential can be restored to a proper potential level. Therefore, high noise tolerance can be obtained.